quartus - Error (10170): Verilog HDL syntax error at filename near text "input"; expecting ";" -

working 2014 version of quartus ii software (web edition), receive error 10170 when compiling following code:

module shifter16 (a, h_sel, h) input [15:0]a; input h_sel; output [15:0]h; reg [15:0] h; @ (a or h_sel) begin     if (h_sel)         h={a[14:0],1'b0};     else         h={a[15],a[15:1]}; end endmodule 

error received:

error (10170): verilog hdl syntax error @ shifter16.v(2) near text "input"; expecting ";"

you need semicolon @ end of first line:

module shifter16 (a, h_sel, h);