SMP boot of ARM Cortex A9 sequence with MMU/cache enabled -

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i trying smp boot in u-boot on dual core arm cortex a9 system mmu/cache enabled. needed sequence of initializations. how should sequence of following things happen. in order?

  • mmu page table setup
  • set smp bit (core 0 , core 1)
  • invalidate cache (inner cache)
  • flushing of cache (inner , outer)
  • when l2 cache must enabled?
  • when scu must enabled? before smp bit or after?

it great help, if can list down sequence of operations.

thanks in advance

this sequence following without issues (like earlier there asynchronous data aborts) main function isn't working, hence debugging on it.

please review , suggest, if stil order or missing.

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