fpga - VHDL beginner - what's going wrong wrt to timing in this circuit? -

i'm new vhdl , hardware design , wondering if tell me if understanding of following problem ran right.

i've been working on simple bcd-to-7 segment display driver nexys4 board - vhdl code (with headers stripped).

entity bcdto7segdriver     port ( clk : in std_logic;            val : in std_logic_vector (31 downto 0);            anode : out std_logic_vector (7 downto 0);            segment : out std_logic_vector (6 downto 0));     function bcd_to_dec7(bcd : std_logic_vector(3 downto 0))        return std_logic_vector    begin        case bcd            when "0000" => return "1000000";            when "0001" => return "1111001";            when "0010" => return "0100100";            when "0011" => return "0110000";            when others => return "1111111";        end case;    end bcd_to_dec7; end bcdto7segdriver;  architecture behavioral of bcdto7segdriver     signal cur_val : std_logic_vector(31 downto 0);     signal cur_anode : unsigned(7 downto 0) := "11111101";     signal cur_seg : std_logic_vector(6 downto 0) := "0000001"; begin  process (clk, val, cur_anode, cur_seg) begin     if rising_edge(clk)         cur_val <= val;         cur_anode <= cur_anode rol 1;         anode <= std_logic_vector(cur_anode);         segment <= cur_seg;     end if;      -- decode segments     case cur_anode         when "11111110" => cur_seg <= bcd_to_dec7(cur_val(3 downto 0));         when "11111101" => cur_seg <= bcd_to_dec7(cur_val(7 downto 4));         when "11111011" => cur_seg <= bcd_to_dec7(cur_val(11 downto 8));         when "11110111" => cur_seg <= bcd_to_dec7(cur_val(15 downto 12));         when "11101111" => cur_seg <= bcd_to_dec7(cur_val(19 downto 16));         when "11011111" => cur_seg <= bcd_to_dec7(cur_val(23 downto 20));         when "10111111" => cur_seg <= bcd_to_dec7(cur_val(27 downto 24));         when "01111111" => cur_seg <= bcd_to_dec7(cur_val(31 downto 28));         when others => cur_seg <= "0011111";     end case; end process; end behavioral; 

now, @ first tried naively drive circuit board clock defined in constraints file:

## clock signal ##bank = 35, pin name = io_l12p_t1_mrcc_35,                 sch name = clk100mhz set_property package_pin e3 [get_ports clk]                              set_property iostandard lvcmos33 [get_ports clk]     create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] 

this gave me looked garbage output on seven-segment displays - looked every decoded digit being superimposed onto every digit place. if bits 3 downto 0 of value being decoded "0001", display showing 8 1s in row instead of 00000001 (but not quite - other segments lit appeared dimmer).

slowing down clock more reasonable did trick , circuit works how expected to.

when @ elaboration gives me (i'm using vivado 2014.1), gives me circuit val connected 8 rtl_roms in parallel (each 1 decoding 4 bits of input). outputs these roms fed rtl_mux , value of cur_anode being used selector. output of rtl_mux feeds cur_val register; cur_val , cur_anode registers linked outputs.

so, in mind, part of circuit couldn't handle clock rate? i've read feel related timing constraints may need add; thinking along right track?

did timing report indicate had timing problem? looks me rolling through segment values extremely fast. no matter how design higher clock speeds, you're rotating cur_anode every clock cycle, , therefore display change accordingly. if clock fast, display change faster human able read it.

some other suggestions:

• you should split single process separate clocked , unclocked processes. it's not you're doing won't end synthesizing (obviously), it's unconventional, , may lead unexpected results.

• your initialization on cur_seg won't anything, it's driven (combinationally) process. it's not problem - wanted make sure aware.