Why is my VHDL detector not recognizing the state change? -

i having problem vhdl code, hope help. see, 'q' signal supposed detect whether state has changed or not, never does. if state never gets 'detecting' 'idle'. q signal remains on '0' value, though state changes, while reset off , clk signal on upper edge. hope see problem is. p.s. state_reg signal state @ moment , next 1 next state. qlevel_detected signal used debugging.

    library ieee;     use ieee.std_logic_1164.all;     use ieee.numeric_std.all;      entity detector     port     (             clk, reset :            in std_logic;             level :                 in std_logic;             q :                     out std_logic;             qlevel_detected :       out std_logic     );     end detector;      architecture behavioral of detector     type state (idle, detecting);     signal state_reg, state_next : state;     signal level_detected_reg, level_detected_next : std_logic;     begin     process(clk, reset)     begin             if (reset = '1')                     state_reg <= idle;             elsif (clk'event , clk = '1')                     state_reg <= state_next;                     level_detected_reg <= level_detected_next;             end if;     end process;      process(state_reg)     begin             state_next <= state_reg;             level_detected_next <= level_detected_reg;      case state_reg             when idle =>                     level_detected_next <= level;                     state_next <= detecting;              when detecting =>                     if (level /= level_detected_reg)                             state_next <= idle;                     end if;     end case;     end process;      -- output logic     q <=    '0' when state_reg = idle else             '1' when state_reg = detecting;      qlevel_detected <= level_detected_reg;     end behavioral;  

your next state process sensitive state_reg. combinational process needs of inputs listed in sensitivity list (or all vhdl-2008).

process(state_reg, level, level_detected_reg) begin ... 

you missing unconditional else on assignment q create latch in synthesis.