vhdl - How to code scoreboard for out-of-order transactions between golden C model and RTL? -

i've uvm test env both golden c++ model , rtl instantiated. in cases c++ model , rtl outputs go out of order c++ model not cycle accurate. in-order outputs, have infinite queues in scoreboard. whenever see output in rtl interface, try match head of c++ model-output queue. here assumption outputs c++ model come before rtl output there no notion of time c++ model.

however things can go crazy , out of order in few scenarios (as example, arbiter). in case, standard way write scoreboard , checking codes in uvm?

here solution assuming transactions can arrive in order, either device under test (dut) or behavioral c++ model.

maintain 2 queues of observed transactions.

• expected -- hold transactions model
• actual -- hold transactions dut

when scoreboard receives transaction dut or model, first check if exists in other queue. if so, found match. otherwise add appropriate queue.

so have:

• on receipt of dut transaction
  • check expected queue match
  • if found, remove expected
  • else, add actual
• on receipt of model transaction
  • check actual queue match
  • if found, remove actual
  • else, add expected

you should verify queues empty @ end of test. , can add other checks depending on requirements. e.g. if expect 1 or 2 items out of order match depth of 1 or 2 in other queue.